The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation of ICs includes smaller and more complex circuits than those of the previous generation. The smaller and more complex circuits are two-dimensional (2D) in nature, in that the area occupied by the integrated IC's components is on the surface of the semiconductor wafer. However, 2DIC formation faces physical limits. One of these limits is the minimum area needed to accommodate the integrated components. In addition, when more devices are included in one chip or die, more complex designs are required.
To enable further increases in circuit density, three-dimensional integrated circuits (3DIC) have been developed. 3DIC package applications such as package-on-package (PoP) are becoming increasingly popular and widely used in mobile devices because they can enhance electrical performance by integrating logic chips (e.g., application processors (APs)), high capacity/bandwidth memory chips (e.g., wide input/output (WIO) chips, low power double data rate X (LPDDRx) chips, and the like), and/or other heterogeneous chips (e.g., sensors, micro-electro-mechanicals (MEMs), networking devices, and the like), for instance.
During the usage of the package, heat is generated. The heat can cause thermal stress and warpage in the 3DIC package structure leading to cracks in the solder balls. Even with molding compounds in the 3DIC package structure, the problems of excess heat and warpage still cannot be entirely eliminated.